模拟和接口芯片

ASM1806

a low latency, low cost and low power 6 lane ,  maximum 4 downstream ports packet switch

ASM1806, a low latency, low cost and low power 6 lane ,  maximum 4 downstream ports PCIE packet switch. With upstream PCIe Gen2x2 bandwidth, ASM1806 can enable  users to build up various high speed IO systems, including server, system storage or communication platforms. 1.1 Features of ASM1806 Upstream PCIe interface  1-, 2- lane PCIe® connecting with root port  Automatic detection of lane configuration on boot-up  Supporting transfer rate of 2.5Gb(250MB/s), 5Gb(500MB/s) per lane Downstream PCIe interface  4 lane PCIe® 2.0 interface supporting up to 4 PCIe® ports  Supported configurations include: Table 1Downstream port configurations Configuration LANE0 LANE1 LANE6 LANE14 1 x1 x1 x1 x1 0 x2 x1 x1  Support L0s/L1/L23/L3 power saving states  Support L1 substate deep power saving mode  Support wake up function in S3/S4  Support LTR  Support AER  Support SRIS on both upstream and downstream ports.  Max Payload Size = 512Byte  Support hot-plug, surprise remove  Package type: 10x10 QFN88

gure 1 ASM1806 Block Diagram CPU (8051) Program ROM (TBD KB) Program RAM (TBD KB) UART SPI Master COM Port SPI Flash MISC GPIO PCIe Host Strapping Pins 25MHz Crystal Crossbar XDATA RAM I2C I2C PCIe PHY (I/II) x2 PCIe Link Transaction Layer PCIe Devices PCIe Link Transaction Layer x4 PCIe PHY (I/II) x4 ASMedia Confid