模拟和接口芯片

ASM2824

ASM2824, a low latency, low cost and low power 24 lane ,  maximum 12 downstream ports PCIE packet switch

ASM2824, a low latency, low cost and low power 24 lane ,  maximum 12 downstream ports packet switch. With upstream PCIe Gen3x8 bandwidth, ASM2824 can enable  users to build up various high speed IO systems, including server, system storage or communication platforms. 1.1 Features of ASM2824 Upstream PCIe interface  1-, 2-, 4-, or 8-lane PCIe® connecting with root port  Automatic detection of lane configuration on boot-up  Supporting transfer rate of 2.5Gb(250MB/s), 5Gb(500MB/s) or 8Gb(1GB/s) per lane Downstream PCIe interface  16 lane PCIe® 3.1 interface supporting up to 12 PCIe® ports  Supported configurations include: Table 1Downstream port configurations Group 0: LANE0~7 Configuration LANE0 LANE1 LANE2 LANE3 LANE4 LANE5 LANE6 LANE7 3'b000 x2 x1 x1 x2 x1 x1 3'b001 x2 x1 x1 x4 3'b010 x4 x2 x1 x1 3'b011 x4 x4 3'b100 x8 Group 1: LANE8~15 Configuration LANE8 LANE9 LANE10 LANE11 LANE12 LANE13 LANE14 LANE15 3'b000 x2 x1 x1 x2 x1 x1 3'b001 x2 x1 x1 x4 3'b010 x4 x2 x1 x1 3'b011 x4 x4 3'b100 x8  Support L0s/L1/L23/L3 power saving states  Support L1 substate deep power saving mode  Support wake up function in S3/S4

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