SPC5748GGK1MMJ6

3*160M 面向汽车电子、工业控制和网关应用的超高可靠性MCU

SPC5748G Microcontroller Data Sheet Features • 2 x 160 MHz Power Architecture® e200Z4 Dual issue, 32-bit CPU – Single precision floating point operations – 8 KB instruction cache and 4 KB data cache – Variable length encoding (VLE) for significant code density improvements • 1 x 80 MHz Power Architecture® e200Z2 Single issue, 32-bit CPU – Using variable length encoding (VLE) for significant code size footprint reduction • End to end ECC – All bus masters, for example, cores generate single error correction, double error detection (SECDED) code for every bus transaction – SECDED covers 64-bit data and 29-bit address • Memory interfaces – 6 MB on-chip flash supported with the flash controller – 3 x flash page buffers (3 port flash controller) – 768 KB on-chip SRAM across three RAM ports • Clock interfaces – 8-40 MHz external crystal (FXOSC) – 16 MHz IRC (FIRC) – 128 KHz IRC (SIRC) – 32 KHz external crystal (SXOSC) – Clock Monitor Unit (CMU) – Frequency modulated phase-locked loop (FMPLL) – Real Time Counter (RTC) • 2x System Memory Protection Unit (SMPU) each with 16 region descriptors and 16-byte region granularity • 16 Semaphores to manage access to shared resource • Interrupt controller (INTC) capable of routing interrupts to any CPU • Multiple crossbar switch architecture for concurrent access to peripherals, flash, and RAM from multiple bus masters • 32-channels eDMA controller with multiple transfer request sources using DMAMUX • Boot Assist Flash (BAF) supports internal flash programming via a serial link (LIN / SCI) • Analog – Two analog-to-digital converters (ADC), one 10-bit and one 12-bit – Three analogue comparators – Cross Trigger Unit to enable synchronization of ADC conversions with a timer event from the eMIOS or from the PIT • Communication – Four Deserial Peripheral Interface (DSPI) – Six Serial Peripheral interface (SPI) – 18 serial communication interface (LIN) modules – Eight enhanced FlexCAN3 with FD support – Four inter-IC communication interface (IIC) – One USB OTG Controller (USB_0) and One USB SPH Controller (USB_1) with ULPI Interface. – ENET complex (10/100 Ethernet) that supports Multi queue with AVB support, 1588, and MII/ RMII – 2 x ENET with L2 switch – Secure Digital Hardware Controller (uSDHC) – Dual-channel FlexRay Controller • Audio – 3 x Synchronous Audio Interface (SAI) – Fractional clock dividers (FCD) operating in conjunction with the SAIs • Configurable I/O domains supporting FLEXCAN, LINFlex, Ethernet, USB, MLB, uSDHC and general I/O • Supports wake-up from low power modes via the WKPU controller • On-chip voltage regulator (VREG) • Debug functionality – e200Z2 core:NDI per IEEE-ISTO 5001-2008 Class3+ – e200Z4 core(s): NDI per IEEE-ISTO 5001

中央车身控制、网关和工业控制应用。