主芯片和MCU

LIFCL-17-7BG256C

LIFCL-17-7BG256C 

CrossLink-NX™ family of low-power FPGAs can be used in a wide range of applications, and are optimized for bridging and processing needs in Embedded Vision applications – supporting a variety of high bandwidth sensor and display interfaces, video processing and machine learning inferencing. It is built on Lattice Nexus FPGA platform, using low-power 28 nm FD-SOI technology. It combines the extreme flexibility of an FPGA with the low power and high reliability (due to extremely low SER) of FD-SOI technology, and offers small footprint package options. CrossLink-NX supports a variety of interfaces including MIPI D-PHY (CSI-2, DSI), LVDS, SLVS, subLVDS, PCI Express (Gen1, Gen2), SGMII (Gigabit Ethernet), andLIFCL-40-7MG121I  Overview Each CrossLink-NX device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) and rows of sysDSP Digital Signal Processing blocks, as shown in Figure 2.1Power Modes – Low Power versus HighPerformance  User selectable  Low-Power mode for power and/or thermal challenges  High-Performance mode for faster processing  Small footprint package options  4 x 4 mm2 to 10 x 10 mm2 package options  2x SGMII CDR at up to 1.25 Gbps – to support 2 channels SGMII using HP I/O  CDR for RX  8b/10b decoding  Independent Loss of Lock (LOL) detector for each CDR block  sysCLOCK™ analog PLLs  Three in 39K LC and two in 17K LC device  Six outputs per PLL  Fractional N  Programmable and dynamic phase control  sysDSP Enhanced DSP blocks  Hardened pre-adder  Dynamic Shift for AI/ML support  Four 18 x 18, eight 9 x 9, two 18 x 36, or 36 x 36  Advanced 18 x 36, two 18 x 18, or four 8 x 8 MAC  Flexible memory resources  Up to 1.5 Mb sysMEM™ Embedded Block RAM (EBR)  Programmable width  ECC  FIFO  80k to 240k bits distributed RAM  Large RAM Blocks  0.5 Mbits per block  Up to five blocks (2.5 Mb total) per device  ALU Features  RISC-V compliant ALU  Register file  SERDES – PCIe Gen2 x1 channel (Tx/Rx) hard IP in 39K LC device  Hard IP supports  Gen1, Gen2, Multi-Function, End Point, Root Complex  APB control bus  AHB-Lite for data bus  Internal bus interface support  APB control bus  AHB-Lite for data bus  AXI4-streaming  Configuration – Fast, Secure  SPI – x1, x2, x4 up to 150 MHz  Master and Slave SPI support  JTAG  I 2C and I3C  Ultrafast I/O configuration for instant-on support  Less than 15 ms full device configuration for LIFCL-40  Bitstream Security  Encryption  Single Event Upset (SEU) Mitigation Support  Extremely low Soft Error Rate (SER) due to FDSOI technology  Soft Error Detect – Embedded hard macro  Soft Error Correction – Without stopping user operation  Soft Error Injection – Emulate SEU event to debug system error handling  ADC – 1 MSPS, 12-bit SAR  2 ADCs per device  3 Continuous-time Comparators  Simultaneous sampling  System Level Support  IEEE 1149.1 and IEEE 1532 compliant  Reveal Logic Analyzer  On-chip oscillator for initialization and general use

 车载自动化，智能设备, 边缘计算，视频人脸识别